1008 search results - page 7 / 202 » A cis-regulatory logic simulator |
VTS
2000
IEEE
14 years 29 days ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
AGI
2008
13 years 10 months ago
2008
Rich computer simulations or quantitative models can enable an agent to realistically predict real-world behavior with precision and performance that is difficult to emulate in log...
FORMATS
2006
Springer
14 years 7 days ago
2006
Springer
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
FORTE
2010
13 years 10 months ago
2010
Abstract. Covariant-contravariant simulation and conformance simulation are two generalizations of the simple notion of simulation which aim at capturing the fact that it is not al...
DAC
1999
ACM
14 years 27 days ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...