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ASPLOS
2011
ACM
12 years 11 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 12 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
HPCA
1998
IEEE
13 years 12 months ago
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
Todd C. Mowy, Charles Q. C. Chan, Adley K. W. Lo
FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
14 years 1 days ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
IPPS
1997
IEEE
13 years 11 months ago
Enhancing Software DSM for Compiler-Parallelized Applications
Current parallelizing compilers for message-passing machines only support a limited class of data-parallel applications. One method for eliminating this restriction is to combine ...
Peter J. Keleher, Chau-Wen Tseng