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» A comparative study of power efficient SRAM designs
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JOCN
2010
70views more  JOCN 2010»
13 years 6 months ago
Optimizing Design Efficiency of Free Recall Events for fMRI
■ Free recall is a fundamental paradigm for studying memory retrieval in the context of minimal cue support. Accordingly, free recall has been extensively studied using behavior...
Ilke Öztekin, Nicole M. Long, David Badre
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 28 days ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
ICCAD
2009
IEEE
93views Hardware» more  ICCAD 2009»
13 years 5 months ago
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Ch...
BMCBI
2008
105views more  BMCBI 2008»
13 years 7 months ago
Using the longest significance run to estimate region-specific p-values in genetic association mapping studies
Background: Association testing is a powerful tool for identifying disease susceptibility genes underlying complex diseases. Technological advances have yielded a dramatic increas...
Ie-Bin Lian, Yi-Hsien Lin, Ying-Chao Lin, Hsin-Cho...
IPPS
2007
IEEE
14 years 1 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson