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» A comparative study of power efficient SRAM designs
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CORR
2010
Springer
196views Education» more  CORR 2010»
13 years 7 months ago
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computin...
H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, ...
ASPDAC
2008
ACM
90views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Vertical via design techniques for multi-layered P/G networks
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...
Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
14 years 8 months ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
WICON
2008
13 years 9 months ago
An experimental study on connectivity and topology control in real multi-hop wireless networks
Topology control by means of transmit power adjustment is a well-studied technique for improving the network capacity and energy efficiency of wireless ad hoc networks. In this pa...
Alvin C. Valera, Pius W. Q. Lee, Yew Fai Wong, Win...
DAC
2001
ACM
14 years 8 months ago
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods
In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on po...
Tsung-Hao Chen, Charlie Chung-Ping Chen