802 search results - page 24 / 161 » A comparative study of power efficient SRAM designs |
ISMVL
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
ECRTS
2004
IEEE
13 years 11 months ago
2004
IEEE
Computing systems, ranging from small battery-operated embedded systems to more complex general purpose systems, are designed to satisfy various computation demands in some accept...
DEDUCTIVE
1994
13 years 9 months ago
1994
Non-deterministic operators are needed in First-Order relational languages and Datalog to extend the expressive power of such languages and support efficient formulations of lowco...
APCSAC
2004
IEEE
13 years 11 months ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...