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» A comparative study of power efficient SRAM designs
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ASPLOS
2006
ACM
13 years 11 months ago
Efficiently exploring architectural design spaces via predictive modeling
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...
Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R...
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
DCC
2008
IEEE
13 years 9 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
VLSISP
2008
159views more  VLSISP 2008»
13 years 7 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
DAC
2000
ACM
14 years 8 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy