Sciweavers

468 search results - page 34 / 94
» A compiler for high performance computing with many-core acc...
Sort
View
BMCBI
2008
211views more  BMCBI 2008»
13 years 7 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
SC
2003
ACM
14 years 26 days ago
A Compiler Analysis of Interprocedural Data Communication
This paper presents a compiler analysis for data communication for the purpose of transforming ordinary programs into ones that run on distributed systems. Such transformations ha...
Yonghua Ding, Zhiyuan Li
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
CF
2007
ACM
13 years 11 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
IPPS
1997
IEEE
13 years 11 months ago
Modeling Compiled Communication Costs in Multiplexed Optical Networks
Improvements in optical technology will enable the constructionof high bandwidth, low latencyswitching networks. These networks have many applications in massively parallel proces...
Charles A. Salisbury, Rami G. Melhem