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MSS
1999
IEEE
112views Hardware» more  MSS 1999»
13 years 12 months ago
HPSS at Los Alamos: Experiences and Analysis
The High Performance Storage System (HPSS) is currently deployed on the open and secure networks at Los Alamos National Laboratory (LANL). Users of the Accelerated Strategic Compu...
Per Lysne, Gary Lee, Lynn Jones, Mark Roschke
ERSA
2004
130views Hardware» more  ERSA 2004»
13 years 9 months ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
12 years 11 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
ESTIMEDIA
2005
Springer
14 years 1 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou