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IAJIT
2010
107views more  IAJIT 2010»
13 years 6 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
FCCM
2006
IEEE
170views VLSI» more  FCCM 2006»
13 years 11 months ago
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems
The Apriori algorithm is a fundamental correlation-based data mining kernel used in a variety of fields. The innovation in this paper is a highly parallel custom architecture impl...
Zachary K. Baker, Viktor K. Prasanna
JPDC
2006
141views more  JPDC 2006»
13 years 7 months ago
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
Secure processor architectures enable new sets of applications such as commercial grid computing, software copy protection and secure mobile agents by providing secure computing e...
Chenghuai Lu, Tao Zhang, Weidong Shi, Hsien-Hsin S...
DEBS
2010
ACM
13 years 11 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
IPPS
2002
IEEE
14 years 17 days ago
Generalized Multipartitioning for Multi-Dimensional Arrays
Multipartitioning is a strategy for parallelizing computations that require solving 1D recurrences along each dimension of a multi-dimensional array. Previous techniques for multi...
Daniel G. Chavarría-Miranda, Alain Darte, R...