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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 1 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
CIDR
2009
167views Algorithms» more  CIDR 2009»
13 years 9 months ago
Unbundling Transaction Services in the Cloud
The traditional architecture for a DBMS engine has the recovery, concurrency control and access method code tightly bound together in a storage engine for records. We propose a di...
David B. Lomet, Alan Fekete, Gerhard Weikum, Micha...
VLDB
2002
ACM
108views Database» more  VLDB 2002»
13 years 8 months ago
Energy-performance trade-offs for spatial access methods on memory-resident data
Abstract. The proliferation of mobile and pervasive computing devices has brought energy constraints into the limelight. Energy-conscious design is important at all levels of syste...
Ning An, Sudhanva Gurumurthi, Anand Sivasubramania...
HPCA
2009
IEEE
14 years 3 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
ICDCS
2007
IEEE
14 years 3 months ago
mTreebone: A Hybrid Tree/Mesh Overlay for Application-Layer Live Video Multicast
Application-layer overlay networks have recently emerged as a promising solution for live media multicast on the Internet. A tree is probably the most natural structure for a mult...
Feng Wang, Yongqiang Xiong, Jiangchuan Liu