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» A connection level model for IEEE 802.11 cells
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DATE
2008
IEEE
118views Hardware» more  DATE 2008»
13 years 9 months ago
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
DATE
2005
IEEE
152views Hardware» more  DATE 2005»
14 years 1 months ago
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis
A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing ana...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...
IPPS
1999
IEEE
13 years 12 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
ASAP
2005
IEEE
165views Hardware» more  ASAP 2005»
14 years 1 months ago
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...
IPPS
2006
IEEE
14 years 1 months ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...