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» A decoupled KILO-instruction processor
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MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
14 years 2 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
JLP
2008
134views more  JLP 2008»
13 years 9 months ago
Backwards type analysis of asynchronous method calls
Asynchronous method calls have been proposed to better integrate object orientation with distribution. In the Creol language, asynchronous method calls are combined with so-called...
Einar Broch Johnsen, Ingrid Chieh Yu
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
13 years 21 days ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
14 years 4 months ago
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
Vasileios Kontorinis, Amirali Shayan, Dean M. Tull...
IEEECIT
2005
IEEE
14 years 3 months ago
A Performance and Power Co-optimization Approach for Modern Processors
In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually...
Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh