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CASES
2008
ACM
13 years 10 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
14 years 5 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
LCPC
2005
Springer
14 years 2 months ago
Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications
Tera-scale high-performance computing has enabled scientists to tackle very large and computationally challenging scientific problems, making the advancement of scientific discov...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
CODES
2010
IEEE
13 years 6 months ago
Statistical approach in a system level methodology to deal with process variation
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
Concepción Sanz Pineda, Manuel Prieto, Jos&...
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 5 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome