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ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 1 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
CORR
2007
Springer
154views Education» more  CORR 2007»
13 years 7 months ago
Application of a design space exploration tool to enhance interleaver generation
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...
JCP
2008
121views more  JCP 2008»
13 years 7 months ago
Towards Design Space Exploration for Biological Systems
For both embedded systems and biological cell systems, design is a feature that defines their identity. The assembly of different components in designs of both systems can vary wid...
Simon Polstra, Tessa E. Pronk, Andy D. Pimentel, T...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 17 days ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 4 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram