102 search results - page 4 / 21 » A design platform for 90-nm leakage reduction techniques |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
TVLSI
2008
13 years 7 months ago
2008
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
TIM
2010
13 years 2 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...