25 search results - page 3 / 5 » A fast parallel reed-solomon decoder on a reconfigurable arc... |
IPPS
1999
IEEE
14 years 3 months ago
1999
IEEE
We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge s...
ARC
2007
Springer
14 years 2 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
PROCEDIA
2010
13 years 5 months ago
2010
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
IEEEPACT
2006
IEEE
14 years 4 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
DASIP
2010
13 years 5 months ago
2010
The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of component...