496 search results - page 8 / 100 » A formal framework for synthesis and verification of logic p... |
POPL
2010
ACM
14 years 6 months ago
2010
ACM
The method of logical relations is a classic technique for proving the equivalence of higher-order programs that implement the same observable behavior but employ different intern...
POPL
2008
ACM
14 years 9 months ago
2008
ACM
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
CORR
2008
Springer
13 years 8 months ago
2008
Springer
Abstract. Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts ...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
14 years 27 days ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
CADE
2007
Springer
14 years 9 months ago
2007
Springer
Abstract. The verification of device drivers is essential for the pervasive verification of an operating system. To show the correctness of device drivers, devices have to be forma...