171 search results - page 14 / 35 » A framework for evaluating design tradeoffs in packet proces... |
ICS
2004
Tsinghua U.
14 years 29 days ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
MOBICOM
2003
ACM
14 years 26 days ago
2003
ACM
Handoff latency results in packet losses and severe End-to-End TCP performance degradation as TCP, perceiving these losses as congestion, causes source throttling or retransmissio...
ICCAD
2003
IEEE
14 years 27 days ago
2003
IEEE
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
APSEC
2000
IEEE
14 years 1 days ago
2000
IEEE
of modelling abstractions to map from items in the real-world to objects in the computational domain is oth for the effective implementation of abstract problem solutions and for ...
DAC
2006
ACM
13 years 9 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...