Sciweavers

246 search results - page 28 / 50
» A functional formalization of on chip communications
Sort
View
DAC
2002
ACM
14 years 7 months ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 1 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
ICMCS
2006
IEEE
146views Multimedia» more  ICMCS 2006»
14 years 25 days ago
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-He...
CASES
2006
ACM
14 years 23 days ago
A network agent for diagnosis and analysis of real-time Ethernet networks
Within the field of automation technology the use of Industrial Ethernet is rising. This in turn demands devices capable of precisely recording, analyzing, and manipulating commu...
Hans-Peter Löb, Rainer Buchty, Wolfgang Karl
HPCA
2002
IEEE
14 years 7 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...