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» A functional formalization of on chip communications
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CODES
2005
IEEE
14 years 2 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
SENSYS
2004
ACM
14 years 2 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
ARITH
2001
IEEE
14 years 7 days ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 8 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
ISAAC
2009
Springer
132views Algorithms» more  ISAAC 2009»
14 years 3 months ago
Hilbert's Thirteenth Problem and Circuit Complexity
We study the following question, communicated to us by Mikl´os Ajtai: Can all explicit (e.g., polynomial time computable) functions f : ({0, 1}w )3 → {0, 1}w be computed by word...
Kristoffer Arnsfelt Hansen, Oded Lachish, Peter Br...