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ENGL
2008
118views more  ENGL 2008»
13 years 8 months ago
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Tera...
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 4 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
ICCAD
2001
IEEE
97views Hardware» more  ICCAD 2001»
14 years 4 months ago
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiova...
OPODIS
2010
13 years 5 months ago
On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors
We consider the problem of scheduling dependent real-time tasks for overloads on a multiprocessor system, yielding best-effort timing assurance. The application/scheduling model in...
Piyush Garyali, Matthew Dellinger, Binoy Ravindran
ICML
2009
IEEE
14 years 8 months ago
Structure learning of Bayesian networks using constraints
This paper addresses exact learning of Bayesian network structure from data and expert's knowledge based on score functions that are decomposable. First, it describes useful ...
Cassio Polpo de Campos, Zhi Zeng, Qiang Ji