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FPT
2005
IEEE
163views Hardware» more  FPT 2005»
14 years 1 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
ECBS
2010
IEEE
151views Hardware» more  ECBS 2010»
14 years 1 months ago
Generating Test Plans for Acceptance Tests from UML Activity Diagrams
The Uniļ¬ed Modeling Language (UML) is the standard to specify the structure and behaviour of software systems. The created models are a constitutive part of the software speciļ¬...
Andreas Heinecke, Tobias Brückmann, Tobias Gr...
ITC
2003
IEEE
172views Hardware» more  ITC 2003»
14 years 1 months ago
First IC Validation of IEEE Std. 1149.6
ā€“This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
Suzette Vandivier, Mark Wahl, Jeff Rearick
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 1 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
DSD
2002
IEEE
93views Hardware» more  DSD 2002»
14 years 29 days ago
Fault Latencies of Concurrent Checking FSMs
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...
Roman Goot, Ilya Levin, Sergei Ostanin