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EUROCAST
2001
Springer
118views Hardware» more  EUROCAST 2001»
14 years 19 days ago
A Language Prototyping Tool Based on Semantic Building Blocks
We present a Language Prototyping System that facilitates the modular development of interpreters from semantic specifications. The theoretical basis of our system is the integrat...
José Emilio Labra Gayo, Juan Manuel Cueva L...
ISSS
1999
IEEE
126views Hardware» more  ISSS 1999»
14 years 13 days ago
Catalyst: A DSIP Design Flow Development in Industry
The Motorola System on Chip Design Technologies (SoCDT) team aims at providing a system design environment for its customers. The Toulouse branch concentrates on design efforts in...
W. De Rammelaere, K. Eckert, T. Lawell, R. McGarit...
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
14 years 8 days ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
14 years 6 days ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
ARC
2007
Springer
150views Hardware» more  ARC 2007»
14 years 4 days ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...