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CAV
2004
Springer
108views Hardware» more  CAV 2004»
15 years 7 months ago
DPLL( T): Fast Decision Procedures
The logic of equality with uninterpreted functions (EUF) and its extensions have been widely applied to processor verification, by means of a large variety of progressively more s...
Harald Ganzinger, George Hagen, Robert Nieuwenhuis...
SDMW
2004
Springer
15 years 7 months ago
Experimental Analysis of Privacy-Preserving Statistics Computation
The recent investigation of privacy-preserving data mining and other kinds of privacy-preserving distributed computation has been motivated by the growing concern about the privacy...
Hiranmayee Subramaniam, Rebecca N. Wright, Zhiqian...
101
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ISCAS
2003
IEEE
91views Hardware» more  ISCAS 2003»
15 years 7 months ago
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity
The full-custom CMOS realization of a new modular sorting architecture is presented. The high-performance architecture is based on rank ordering, and on efficient implementation o...
Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
115
Voted
MSE
2003
IEEE
104views Hardware» more  MSE 2003»
15 years 7 months ago
Internet-based Tool for System-on-Chip Integration
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...
David Lim, Christopher E. Neely, Christopher K. Zu...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 7 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...