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ICS
2001
Tsinghua U.
15 years 6 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 6 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
120
Voted
VLSID
1999
IEEE
101views VLSI» more  VLSID 1999»
15 years 6 months ago
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
Ingo Sander, Axel Jantsch
CODES
1999
IEEE
15 years 6 months ago
System synthesis utilizing a layered functional model
We propose a system synthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is...
Ingo Sander, Axel Jantsch
DATE
2009
IEEE
249views Hardware» more  DATE 2009»
15 years 9 months ago
White box performance analysis considering static non-preemptive software scheduling
—In this paper, a novel approach for integrating static non-preemptive software scheduling in formal bottom-up performance evaluation of embedded system models is described. The ...
Alexander Viehl, Michael Pressler, Oliver Bringman...