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ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 4 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efļ¬...
Yau Chin, John Sheu, David Brooks
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
14 years 2 months ago
Double-sampling single-loop sigma-delta modulator topologies for broadband applications
This paper presents novel double sampling high order single-loop sigma-delta modulator structures for wideband applications. To alleviate the quantization noise folding into the i...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
DATE
2010
IEEE
138views Hardware» more  DATE 2010»
14 years 1 months ago
Checking and deriving module paths in Verilog cell library descriptions
ā€”Module paths are often used to specify the delays of cells in a Verilog cell library description, which deļ¬ne the propagation delay for an event from an input to an output. Sp...
Matthias Raffelsieper, Mohammad Reza Mousavi, Chri...
CAV
1998
Springer
138views Hardware» more  CAV 1998»
14 years 5 days ago
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
bstract description of state machines (ASMs), in which data and data operations are d using abstract sort and uninterpreted function symbols. ASMs are suitable for describing Regis...
Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Core...
CAV
2010
Springer
173views Hardware» more  CAV 2010»
13 years 11 months ago
A Model Checker for AADL
We present a graphical toolset for verifying AADL models, which are gaining widespread acceptance in aerospace, automobile and avionics industries for comprehensively specifying sa...
Marco Bozzano, Alessandro Cimatti, Joost-Pieter Ka...