Sciweavers

1013 search results - page 87 / 203
» A hardware implementation of realloc function
Sort
View
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 27 days ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
SAFECOMP
2007
Springer
14 years 2 months ago
Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer
This paper presents an experimental evaluation of the fault-tolerant communication (FTCOM) layer of the DECOS integrated architecture. The FTCOM layer implements different agreemen...
Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bern...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
13 years 10 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch
FPL
2007
Springer
128views Hardware» more  FPL 2007»
14 years 2 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton
IWSOC
2005
IEEE
133views Hardware» more  IWSOC 2005»
14 years 1 months ago
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip
This paper presents a case study of a single-chip 3G WCDMA/FDD basestation implementation based on a circuit-switched network on chip. As the amount of transistors on a chip conti...
Daniel Wiklund, Dake Liu