70 search results - page 9 / 14 » A hardware software partitioning algorithm for pipelined ins... |
CGO
2003
IEEE
14 years 10 hour ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
SBCCI
2005
ACM
14 years 8 days ago
2005
ACM
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
ACMMSP
2004
ACM
14 years 4 days ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ERSA
2004
13 years 8 months ago
2004
Advanced multimedia applications (e.g. based on MPEG-4) will consist of multiple scalable multimedia objects. This scalability enables the application to adapt to different proces...