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» A high performance JPEG2000 architecture
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DAC
1995
ACM
13 years 11 months ago
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs
A new approa ch for pe r f or ma nc e -dr ive n r outi ng i n hi ghly c onge st e d hi gh s pe e d MCMs a nd PCBs i s pr e s e nt e d. Gl oba l r out i ng i s e mpl oye d t o ma n...
Sharad Mehrotra, Paul D. Franzon, Michael Steer
SAMOS
2010
Springer
13 years 6 months ago
Interleaving granularity on high bandwidth memory architecture for CMPs
—Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip m...
Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex...
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
14 years 3 days ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
SC
2004
ACM
14 years 1 months ago
Experiences in Design and Implementation of a High Performance Transport Protocol
This paper describes our experiences in the development of the UDP-based Data Transport (UDT) protocol, an application level transport protocol used in distributed data intensive ...
Yunhong Gu, Xinwei Hong, Robert L. Grossman
HOTI
2005
IEEE
14 years 1 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner