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ISCAS
2007
IEEE
139views Hardware» more  ISCAS 2007»
14 years 2 months ago
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
ICSE
2003
IEEE-ACM
14 years 7 months ago
A Component Architecture for an Extensible, Highly Integrated Context-Aware Computing Infrastructure
Ubiquitous context-aware computing systems present several challenges in their construction. Principal among them is the tradeoff between easily providing new contextaware service...
William G. Griswold, Robert T. Boyer, Steven W. Br...
GRID
2004
Springer
14 years 1 months ago
DIRAC: A Scalable Lightweight Architecture for High Throughput Computing
— DIRAC (Distributed Infrastructure with Remote Agent Control) has been developed by the CERN LHCb physics experiment to facilitate large scale simulation and user analysis tasks...
Andrei Tsaregorodtsev, Vincent Garonne, Ian Stokes...
CBSE
2004
Springer
14 years 1 months ago
Software Architectural Support for Disconnected Operation in Highly Distributed Environments
: In distributed and mobile environments, the connections among the hosts on which a software system is running are often unstable. As a result of connectivity losses, the overall ...
Marija Mikic-Rakic, Nenad Medvidovic
IPPS
2007
IEEE
14 years 2 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson