2209 search results - page 78 / 442 » A high performance JPEG2000 architecture |
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
ICASSP
2011
IEEE
13 years 1 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
SBCCI
2005
ACM
14 years 3 months ago
2005
ACM
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
IPPS
1999
IEEE
14 years 2 months ago
1999
IEEE
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
RTSS
2008
IEEE
14 years 4 months ago
2008
IEEE
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...