159 search results - page 22 / 32 » A high throughput 3D-bus interconnect for network processors |
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
PDP
2005
IEEE
14 years 28 days ago
2005
IEEE
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...