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» A high throughput 3D-bus interconnect for network processors
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CAL
2008
13 years 7 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
IPPS
1999
IEEE
13 years 11 months ago
NetCache: A Network/Cache Hybrid for Multiprocessors
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
Enrique V. Carrera, Ricardo Bianchini
SPAA
2004
ACM
14 years 23 days ago
Adaptive channel queue routing on k-ary n-cubes
This paper introduces a new adaptive method, Channel Queue Routing (CQR), for load-balanced routing on k-ary n-cube interconnection networks. CQR estimates global congestion in th...
Arjun Singh, William J. Dally, Amit K. Gupta, Bria...
CLUSTER
2006
IEEE
14 years 1 months ago
Cluster-based IP Router: Implementation and Evaluation
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...
Qinghua Ye, Mike H. MacGregor
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
14 years 28 days ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...