Sciweavers

159 search results - page 27 / 32
» A high throughput 3D-bus interconnect for network processors
Sort
View
GLOBECOM
2006
IEEE
14 years 1 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
CCGRID
2004
IEEE
13 years 11 months ago
GTP: group transport protocol for lambda-Grids
The notion of lambda-Grids posits plentiful collections of computing and storage resources richly interconnected by dedicated dense wavelength division multiplexing (DWDM) optical...
Xinran (Ryan) Wu, Andrew A. Chien
ICPADS
2002
IEEE
14 years 8 days ago
Self-Stabilizing Wormhole Routing on Ring Networks
Wormhole routing is most common in parallel architectures in which messages are sent in small fragments called flits. It is a lightweight and efficient method of routing message...
Ajoy Kumar Datta, Maria Gradinariu, Anthony B. Ken...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 2 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
EUROPAR
2001
Springer
13 years 12 months ago
VIA Communication Performance on a Gigabit Ethernet Cluster
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
Mark Baker, Paul A. Farrell, Hong Ong, Stephen L. ...