159 search results - page 6 / 32 » A high throughput 3D-bus interconnect for network processors |
CF
2004
ACM
14 years 23 days ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
IEEEPACT
2003
IEEE
14 years 18 days ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
HIPEAC
2005
Springer
14 years 26 days ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
ANCS
2009
ACM
13 years 5 months ago
2009
ACM
Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...