315 search results - page 47 / 63 » A low complexity hardware architecture for motion estimation |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
ACSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose an architecture of four complimentary technologies increasingly relevant to a growing number of home users and organizations: cryptography, separation kernels, formal v...
ICIP
2007
IEEE
14 years 9 months ago
2007
IEEE
We propose a method for delivering error-resilient video from wireless camera networks in a distributed fashion over lossy channels. Our scheme is based on distributed source codi...