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IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 2 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 4 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
DSD
2008
IEEE
147views Hardware» more  DSD 2008»
13 years 9 months ago
A Low-Cost Cache Coherence Verification Method for Snooping Systems
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
Demid Borodin, Ben H. H. Juurlink
RTAS
2010
IEEE
13 years 6 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
MICRO
2009
IEEE
128views Hardware» more  MICRO 2009»
14 years 2 months ago
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity...
Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramach...