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» A low power FPGA routing architecture
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JUCS
2006
140views more  JUCS 2006»
13 years 7 months ago
A Modular Architecture for Nodes in Wireless Sensor Networks
: The growth of sensor networks during the last years is a fact and within this field, wireless sensor networks are growing particularly as there are many applications that demand ...
Jorge Portilla, Angel de Castro, Eduardo de la Tor...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
14 years 1 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
FPGA
2003
ACM
156views FPGA» more  FPGA 2003»
14 years 17 days ago
Architectures and algorithms for synthesizable embedded programmable logic cores
As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programm...
Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton
ASPDAC
2005
ACM
122views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...
Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lind...
CODES
2006
IEEE
14 years 1 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha