90 search results - page 17 / 18 » A low power FPGA routing architecture |
SPAA
2003
ACM
14 years 17 days ago
2003
ACM
We propose a new approach for constructing P2P networks based on a dynamic decomposition of a continuous space into cells corresponding to servers. We demonstrate the power of thi...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
CDES
2006
13 years 8 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ICES
2010
Springer
13 years 5 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
SENSYS
2003
ACM
14 years 17 days ago
2003
ACM
Wireless sensor networks promise fine-grain monitoring in a wide variety of environments. Many of these environments (e.g., indoor environments or habitats) can be harsh for wire...