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VLSID
1996
IEEE
13 years 11 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— In this paper, an innovative frequency domain joint estimation algorithm of synchronization parameter and channel impulse response (CIR) in Direct Sequence Code Division Multip...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
ISLPED
2009
ACM
14 years 17 hour ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
SBCCI
2003
ACM
14 years 18 days ago
2003
ACM
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...