45 search results - page 6 / 9 » A low-power clock frequency multiplier |
ACSAC
2000
IEEE
14 years 2 months ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
– We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique ...
ISCAS
2008
IEEE
14 years 4 months ago
2008
IEEE
— A low energy modulo-multiplier is proposed for elliptic curve cryptography (ECC) processor, especially for authentication in mobile device or key encryption in embedded health-...
VLSID
2003
IEEE
14 years 10 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...