357 search results - page 28 / 72 » A methodology for the selection of requirements engineering ... |
ATS
2010
IEEE
13 years 5 months ago
2010
IEEE
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
AVI
2008
13 years 10 months ago
2008
Many critical decisions for individuals and organizations are often framed as preferential choices: the process of selecting the best option out of a set of alternatives. This pap...
AOSE
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. Nowadays, information systems have to perform in complex, heterogeneous environments, considering a variety of system users with different needs and preferences. Software...
CODES
2008
IEEE
13 years 9 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...