76 search results - page 3 / 16 » A methodology to improve timing yield in the presence of pro... |
PATMOS
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
CODES
2010
IEEE
13 years 6 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
DAC
2010
ACM
14 years 14 days ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
ICIP
2003
IEEE
14 years 10 months ago
2003
IEEE
In this paper the blind image deconvolution (BID) problem is solved using the Bayesian framework. In order to find the parameters of the proposed Bayesian model we present a new g...