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ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
14 years 1 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
IJAOSE
2008
120views more  IJAOSE 2008»
13 years 7 months ago
An architecture for exception management in multiagent systems
: Multiagent Systems (MAS) are open, heterogeneous and distributed software systems of autonomous agents. The management of exception differs in MAS from what is known in usual eng...
Eric Platon, Nicolas Sabouret, Shinichi Honiden
ICCD
2002
IEEE
109views Hardware» more  ICCD 2002»
14 years 4 months ago
Physical Planning Of On-Chip Interconnect Architectures
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand fo...
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
NAACL
2007
13 years 9 months ago
An Integrated Architecture for Speech-Input Multi-Target Machine Translation
The aim of this work is to show the ability of finite-state transducers to simultaneously translate speech into multiple languages. Our proposal deals with an extension of stocha...
Alicia Pérez, Maria-Teresa González,...
ETFA
2008
IEEE
14 years 2 months ago
Reactivity analysis of different Networked Automation System architectures
The reactivity of Networked Automation Systems (NAS) has direct influence on safety and quality aspects. It can be determined by a response time analysis, which itself can be calc...
Jürgen Greifeneder, Georg Frey