155 search results - page 13 / 31 » A new heuristic algorithm for reversible logic synthesis |
FPGA
2004
ACM
14 years 27 days ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
CEC
2003
IEEE
13 years 11 months ago
2003
IEEE
Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biologi...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
OOPSLA
2010
Springer
13 years 6 months ago
2010
Springer
Given a high-level specification and a low-level programming language, our goal is to automatically synthesize an efficient program that meets the specification. In this paper,...