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» A new heuristic algorithm for reversible logic synthesis
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DAC
2007
ACM
14 years 8 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ISMVL
2003
IEEE
68views Hardware» more  ISMVL 2003»
14 years 22 days ago
Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades
Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary To...
Mozammel H. A. Khan, Marek A. Perkowski, Pawel Ker...
DAC
2005
ACM
14 years 8 months ago
A new canonical form for fast boolean matching in logic synthesis and verification
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Afshin Abdollahi, Massoud Pedram
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
13 years 11 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski