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EACL
2009
ACL Anthology
14 years 8 months ago
The Software Architecture for the First Challenge on Generating Instructions in Virtual Environments
The GIVE Challenge is a new Internetbased evaluation effort for natural language generation systems. In this paper, we motivate and describe the software infrastructure that we de...
Alexander Koller, Donna Byron, Justine Cassell, Ro...
PPOPP
1990
ACM
13 years 12 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
14 years 2 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
IPPS
2006
IEEE
14 years 1 months ago
Empowering a helper cluster through data-width aware instruction selection policies
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- a...
Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio G...