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APCCAS
2002
IEEE
95views Hardware» more  APCCAS 2002»
14 years 22 days ago
Reducing power consumption of instruction ROMs by exploiting instruction frequency
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the sw...
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
14 years 2 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
13 years 12 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
COMPSAC
2005
IEEE
14 years 1 months ago
Considerations on a New Software Architecture for Distributed Environments Using Autonomous Semantic Agents
Distributed processing environments such as that of a traffic management network system (TMS) can be implemented easier, faster, and secure and perform better through use of auton...
Atilla Elçi, Behnam Rahnama