179 search results - page 22 / 36 » A new test pattern generation method for delay fault testing |
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
DAC
2000
ACM
13 years 12 months ago
2000
ACM
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...