179 search results - page 24 / 36 » A new test pattern generation method for delay fault testing |
140
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ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
154
Voted
DAC
2003
ACM
15 years 8 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
149
Voted
TCAD
2011
14 years 10 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
147
Voted
DFT
2002
IEEE
15 years 8 months ago
2002
IEEE
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
113
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...